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Alif Semiconductor /AE512F80F55D5AS_CM55_HE_View /CLKCTL_SYS /HOSTCPUCLK_DIV1

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Interpret as HOSTCPUCLK_DIV1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)CLKDIV0 (Val_0x0)CLKDIV_CUR

CLKDIV_CUR=Val_0x0, CLKDIV=Val_0x0

Description

APSS_CLK Clock Divider 1 Register

Fields

CLKDIV

Select the value of the integer divider applied to CPUPLL_CLK

0 (Val_0x0): Divide by 1

1 (Val_0x1): Divide by 2

31 (Val_0x1F): Divide by 32
CLKDIV_CUR

Current value of integer divider applied to CPUPLL_CLK

0 (Val_0x0): Divided by 1

1 (Val_0x1): Divided by 2

31 (Val_0x1F): Divided by 32

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data